AMD introduces 2nm Epyc Venice with 256 cores for next-gen AI and cloud workloads

AMD's 2nm Epyc Venice CPU with 256 cores advances AI and cloud workloads for 2026.

: AMD is introducing the Epyc Venice processor, built on the Zen 6 architecture, promising vast improvements in server computing for AI and cloud tasks. Slated for 2026, the Venice CPU features 256 cores, a 33% increase over its predecessor, offering 70% higher performance due to increased efficiency. Utilizing TSMC’s 2nm process, it enhances energy efficiency while doubling per-socket memory bandwidth and CPU-to-GPU communication. This debut on the new SP7 platform supports expanded power, I/O demands, and features both standard and Zen 6c versions up to 256 cores, anchoring AMD's Helios architecture.

The new AMD Epyc Venice processor is poised to redefine the standards in data center processing. Unveiled at AMD’s Advancing AI event, Venice is built using the Zen 6 architecture and is expected to hit the market in 2026. This innovative chip's primary focus is meeting the increased demands of artificial intelligence processing, cloud computing, and high-performance data analytics. A key component in meeting these demands comes from the 256-core count, a substantial improvement over the current Epyc Turin processors' 192 cores.

AMD claims Venice will perform 70% faster than its predecessor, achieved by not only incorporating more cores but also enhancing per-core efficiency and architectural improvements. Such improvements are facilitated through TSMC's 2nm node, which represents a significant leap by bypassing the 4nm process to introduce a denser, more efficient design. This facilitates packing more transistors in the CPU, enhancing both performance and energy efficiency.

Another critical feature is the increased memory bandwidth, which is set to rise from 614 gigabytes per second to 1.6 terabytes per second via support for 16 channels of DDR5 memory. Additionally, advanced memory technologies like MR-DIMM and MCR-DIMM contribute to this performance leap, which is particularly beneficial for data-heavy AI workload processing. This increase plays a crucial role in feeding data to the numerous high-performance cores, making the Venice CPU suited for data-intensive applications.

The advancements extend to connectivity, with Venice doubling the bandwidth for CPU-to-GPU communication through what is expected to be PCI Express 6.0, offering up to 128 PCIe lanes for moving data swiftly in AI tasks. This is crucial in accelerating AI training and inference due to rapid data movement between processors and graphical processing units.

The Venice processor will be introduced on the new SP7 platform, which supports enhanced power and input/output demands, accommodating an upgrade beyond the 700 watts supported by the present SP5 platform. The new platform offers greater expansion potential, aiding more compute complex dies and additional memory channels. Additionally, AMD will introduce two primary variants: a standard Zen 6 with up to 96 cores and a high-density Zen 6c with up to 256 cores, both supporting up to 512 threads.

Looking forward, Venice is expected to serve as the centerpiece of AMD's Helios rack-scale architecture, integrating the new CPUs with Instinct MI400 GPUs and next-gen networking. This strategy is anticipated to substantially increase AI efficiencies and memory capabilities, ensuring AMD remains a key player in tech advancement.

Sources: TechSpot, Tom's Hardware

TechnologyAICloud