DRAM manufacturers explore new designs to overcome 3D stacking hurdles

3D DRAM development continues, focusing on innovative designs like capacitor-less and vertical transistor methods.

: DRAM manufacturers are exploring new designs to overcome challenges in 3D stacking. Efforts include horizontal capacitors, capacitor-less designs, and advanced lithography. The aim is to enhance memory density and efficiency, benefiting data centers and AI applications. These developments, though promising, will require years of research before commercial viability.

DRAM manufacturers are actively seeking new ways to address obstacles in 3D stacking, much like the advancements made by flash memory in monolithic 3D processing. A particular focus is on solving the issue posed by the thick layers created by traditional vertical capacitors, leading to exploration of horizontal capacitors and even designs without capacitors altogether.

Experts like Benjamin Vincent from Lam Research highlight that evolving DRAM to three dimensions increases storage per unit area, reducing production costs. A move towards advanced lithography techniques is also being made, with EUV patterning competing against traditional ArF SADP and SAQP processes as a means to shrink feature sizes and optimize DRAM cells.

Promising designs include Samsung's work on a 4F2 cell architecture using ferroelectrics and Neo Semiconductor's floating-body cell with dual gating. Despite these innovations, stakeholders like Daniel Soden note the lengthy development timeline required before 3D DRAM can achieve commercial traction, emphasizing the challenges posed by new architectures compared to existing methodologies.

DRAM3D stackingSemiconductors