Intel Arrow Lake-S CPU gets delidded ahead of launch, showcasing tiled architecture

Intel Arrow Lake-S CPU shows chiplet design in delidded photos by Madness727.

: Intel's Arrow Lake-S CPU was delidded by hardware enthusiast Madness727, revealing its tiled architecture. The CPU features a chiplet design with 8 performance and 16 efficiency cores, 4 Xe GPU cores, and other essential tiles. It uses various process nodes for different tiles, optimizing performance. This design aids performance-per-watt and component upgrades.

Intel's Arrow Lake-S CPU has been delidded ahead of its official launch by streamer Madness727, revealing its innovative tiled architecture. This unveiling gave the first real-world view of the chiplet design, which includes a compute tile with 8 Lion Cove performance cores and 16 Skymont efficiency cores.

The graphics capabilities are supported by a graphics tile with 4 Xe GPU cores, and other functions are integrated into I/O and SoC tiles with a Thunderbolt 4 controller. An unusual feature is an empty 'dummy' tile, seemingly present for structural support. These various components are manufactured using different process nodes, including TSMC's advanced N3B and N5P nodes for the compute and GPU tiles, respectively.

The desktop Arrow Lake-S models employ a 5-tile layout, benefiting from Intel's assembly of the tiles on a base layer using 22nm FinFET technology. This chiplet architecture improves performance-per-watt and allows easier integration of new components for future upgrades. For mobile Arrow Lake-H chips, slated for Q1 2025, a more streamlined configuration is planned, featuring reduced compute and expanded graphics capabilities.

Intel CPUchiplet architecturehardware